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Sheet目录3873

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dsPIC33F

DS70165E-page 172

Preliminary

2007 Microchip Technology Inc.

14.3

Pulse-Width Modulation Mode

The following steps should be taken when configuring

the output compare module for PWM operation:

Set the PWM period by writing to the selected

Timer Period register (PRy).

Set the PWM duty cycle by writing to the OCxRS

Write the OxCR register with the initial duty cycle.

Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utilization.

Configure the output compare module for one of

two PWM operation modes by writing to the Out-

put

Compare

Mode

bits,

OCM<2:0>

(OCxCON<2:0>).

Set the TMRy prescale value and enable the

time base by setting TON = 1 (TxCON<15>).

14.3.1

PWM PERIOD

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 14-1:

EQUATION 14-1:

CALCULATING THE PWM

PERIOD

14.3.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the OCxRS

but the duty cycle value is not latched into OCxR until a

match between PRy and TMRy occurs (i.e., the period is

complete). This provides a double buffer for the PWM duty

cycle and is essential for glitchless PWM operation. In the

PWM mode, OCxR is a read-only register.

Some important boundary parameters of the PWM duty

cycle include:

If the Output Compare register, OCxR, is loaded

with 0000h, the OCx pin will remain low (0% duty

cycle).

If OCxR is greater than PRy (Timer Period register),

the pin will remain high (100% duty cycle).

If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other count values.

See Example 14-1 for PWM mode timing details.

Table 14-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

EQUATION 14-2:

CALCULATION FOR MAXIMUM PWM RESOLUTION

EXAMPLE 14-1:

PWM PERIOD AND DUTY CYCLE CALCULATIONS

Note:

The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

read-only duty cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Output Compare

Secondary register, OCxRS, will not be

transferred into OCxR until a time base

period match occurs.

Note:

A PRy value of N will produce a PWM

period of N + 1 time base count cycles. For

example, a value of 7 written into the PRy

eight time base cycles.

PWM Period = [(PRy) + 1] TCY (Timer Prescale Value)

PWM Frequency = 1/[PWM Period]

where:

(

)

Maximum PWM Resolution (bits) =

FCY

FPWM

log10

log10(2)

bits

Find the Timer Period register value for a desired PWM frequency that is 52.08 kHz, where FCY = 16 MHz and a Timer2

prescaler setting of 1:1.

TCY

= 62.5 ns

PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2

μs

PWM Period = (PR2 + 1) TCY (Timer2 Prescale Value)

19.2

μs

= (PR2 + 1) 62.5 ns 1

PR2

= 306

Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:

PWM Resolution

log10(FCY/FPWM)/log102) bits

=(log10(16 MHz/52.08 kHz)/log102) bits

8.3 bits

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